Z89139 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z89139

VOICE PROCESSING CONTROLLERS

Zilog 

Zilog

Z89138/Z89139

Voice Processing Controllers

DSP Interrupts

and INT0, respectively (Figure 34). The DSP does not al-

The DSP processor has three interrupt sources (INT2,

INT1, INT0) (Figure 32). These sources have different pri-

ority levels (Figure 33). The highest priority, the next lower

and the lowest priority level are assigned to INT2, INT1

low interrupt nesting (interrupting service routines that are

currently being executed). When two interrupt requests oc-

cur simultaneously the DSP starts servicing the interrupt

with the highest priority level.

1

Z8_INT

A/D INT

D/A INT

IPR2

IPR1

IPR0

FB DSP

Interrupt Priority Logic

Interrupt Request Logic

FeedBack Z8_INT MPX

INT2

INT1

INT0

Interrupt Mask Logic

INT2

INT1

INT0

CLEAR_INT0

CLEAR_INT1

CLEAR_INT2

ENABLE_INT

Figure 32. DSP Interrupts

INT0

INT1

INT2

DSP Execution

INT2

INT0

INT1

INT2

Figure 33. DSP Interrupt Priority Structure

Z8 Side

On the Z8, set D1 to

interrupt DSP via DSP INT2.

DSP CON

After serving IRQ3,

set D0 to clear the

interrupt request.

IRQ3 of the Z8

10

9

DSP Side

DSP INT2

After serving INT2,

set D4 to clear the

interrupt request.

4

ICR

(EXT4)

The DSP sets D9 to

interrupt Z8 via Z8 IRQ3.

Figure 34. Interprocessor Interrupts Structure

DS97TAD0201

PRELIMINARY

45

Share Link: