Z89139 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z89139

VOICE PROCESSING CONTROLLERS

Zilog 

Zilog

Z89138/Z89139

Voice Processing Controllers

Interrupt Control Register (ICR). The ICR is mapped into routine executed on the Z8 side, the User must reset the

EXT4 of the DSP (Table 15). The bits are defined as fol- Z8_IRQ3 bit by writing a 1 to bit D0 of the DSPCON.

lows:

1 The hardware of the Z89138/139 automatically resets

DSP_IRQ2 (Z8 Interrupt). This bit is read by both Z8 and Z8_IRQ3 bit three instructions of the Z8 after 1 is written to

DSP and is set only by writing to the Z8 expanded Register its location in register bank 0F. This delay provides the tim-

File (Bank F, ROC, bit 0). This bit asserts IRQ2 of the DSP ing synchronization between the Z8 and the DSP sides

and is cleared by writing to the Clear_IRQ2 bit.

during interrupts. In summary, the interrupt service routine

of the Z8 for IRQ3 should be finished by:

DSP_IRQ1 (A/D Interrupt). This bit is read by the DSP only

and is set when valid data is present at the A/D output reg- LD ; RP,#%0F

ister (conversion done). This bit asserts IRQ1 of the DSP OR ; r12,#%01

and is cleared by writing to the Clear_IRQ1bit.

POP ; RP

IRET ;

DSP_IRQ0 (D/A Interrupt). This bit is read by DSP only

and is set by Timer3. This bit assists IRQ0 of the DSP and DSP Enable_INT. Writing a 1 to this location enables glo-

is cleared by writing to the Clear_IRQ0 bit.

bal interrupts of the DSP while writing 0 disables them. A

system Reset globally disables all interrupts.

DSP_MaskIntX. These bits are accessed by the DSP

only. Writing a 1 to these locations allows the INT to be DSP_IPRX. This three-bit group defines the Interrupt Se-

serviced, while writing a 0 masks off the corresponding lection logic as shown in Table 16.

INT.

Clear_IRQX. These bits are accessed by the DSP only.

Z8_IRQ3. This bit can be read by both the Z8 and the DSP Writing a 1 to these locations resets the corresponding

but can only be set by the DSP. Addressing this location DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are

accesses bit D3 of the Z8 IRQ register, hence, this bit is not implemented.

not implemented in the ICR. During the interrupt service

DSP_IPR[2-0]

210

000

001

010

011

100

101

110

111

Table 16. DSP Interrupt Selection

Z8_INT is

switched to

INT2

INT1

INT2

INT1

INT0

INT0

Reserved

Reserved

A/D_INT is

switched to

INT1

INT2

INT0

INT0

INT2

INT1

Reserved

Reserved

D/A_INT is

switched to

INT0

INT0

INT1

INT2

INT1

INT2

Reserved

Reserved

DS97TAD0201

PRELIMINARY

47

Share Link: