CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.6 Switching Characteristics— RESET
Parameter
RESET# minimum pulse width low
All bidirectional pins high-Z after RESET# low
Configuration pins setup before RESET# high
Configuration pins hold after RESET# high
Symbol
Min
Trstl
1
Trst2z
-
Trstsu
50
Trsthld
20
Max
Unit
-
µs
100
ns
-
ns
-
ns
RESET#
HS[3:0]
All Bidirectional
Pins
Trst2z
Trstl
Trstsu Trsthld
DRAFT
CONFIDENTDIEALLPHI Figure 1. RESET Timing
14
©Copyright 2006 Cirrus Logic, Inc.
DS734A3
CONFIDENTIAL