TDA7580(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA7580 Datasheet PDF : 31 Pages
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TDA7580
I2C INTERFACES
The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C
bus compatible devices incorporate an on-chip interface which allows them communicate directly with each oth-
er via the I2C bus.
Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some
other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality.
Two pins are used to interface both I2C of the DSP and RDS, which have different internal I2C address, thus
reducing the on-board pin interconnections.
SERIAL PERIPHERAL INTERFACES
The DSP and RDS can have this serial interface, alternative to the I2C one. DSP and RDS SPI modules have
separate pin for chip select.
The DSP SPI has a ten 24bit-words deep FIFO for both receive and transmit sections, which reduces DSP pro-
cessing overhead even at high data rate.
The serial interface is needed to exchange commands and data over the LAN. During an SPI transfer, data is
transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the informa-
tion on the two serial data lines. A slave select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simulta-
neously shifted in a second data pin.The central element in the SPI system is the shift register and the read data
buffer. The system is single buffered in the transfer direction and double buffered in the receive direction.
HIGH SPEED SERIAL SYNCHRONOUS INTERFACE (HS3I)
The High Speed Serial Synchronous Interface is a module to send and receive data at high rate (up to 9.25Mbit/
s per channel) in order to exchange data between 2 separate TDA7580 chip.
The exchanged data are related to signals that are used to increase reception quality in Car Radio systems,
which make use of Antenna Diversity based upon two separate antenna and tuner sections.
The channel synchronization clock has a programmable duty cycle, so to reduce in-band harmonics noise.
TUNER AGC KEYING DAC (KEYDAC)
This DAC provides the front-end tuner with an analogue signal to be used to control the Automatic Gain Con-
trolled stage, thus giving all time the best voltage dynamic range at the IFADC input.
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC)
This hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external
source. It does not require further work off the DSP.
There is no need to explicitly configure the input and the output sample rates, as the ASRC solves this problem
with an automatic Digital Ratio Locked Loop.
Main features are:
s Automatic Tracking of Sample Frequency
s Fully Digital Ratio Locked Loop
s Sampling Clock Jitter Rejection
s Up-conversion up to 1:2 Ratio
s Linear Phase
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