TDA7580(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA7580 Datasheet PDF : 31 Pages
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TDA7580
IF BAND PASS SIGMA DELTA ANALOGUE TO DIGITAL CONVERTER (IFADC)
The IFADC is a Band Pass Sigma Delta A to D converter with sampling rate of 37.05MHz (nominal) and notch
frequency of 10.7MHz. The structure is a second order switched capacitor multi bit modulator with self calibra-
tion algorithm to adjust the notch frequency.
The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred noise back to the
previous stage (tuner), and in turn gives high rejection to common mode noises.
The high linearity (very high IMD) is needed to fulfill good response of the channel equalization algorithm.
Low thermal and 1/f noise assures high dynamic range.
DIGITAL DOWN CONVERTER (DDC)
The DDC module allows to evaluate the in-phase and quadrature components of the incoming digital IF signal.
The I and Q computation is performed by the DDC block, which at the same time shifts down to 0-IF frequency
the incoming digital signal.
After the down conversion the rate is still very high (at the 37.05MHz rate); a SincK filter samples data down by
a factor of 32, decreasing it to 1.1578MHz. An additional decimation is performed by the subsequent FIR filters,
thus lowering the data rate at the final 289.45kHz, being the MPX data rate.
RDS
The RDS block is an hardware cell able to process RDS/RBDS signal, intended for recovering the inaudible
RDS/RBDS information which are transmitted by most of FM radio broadcasting stations.
It comprises of the following:
s Demodulation of the European Radio Data System (RDS)
s Demodulation of the US Radio Broadcast Data System (RDBS)
s Automatic Group and Block synchronisation with flywheel mechanism
s Error Detection and Correction
s RAM buffer with a storage capacity of 24 RDS blocks and related status information
s I2C and SPI interface, with pins shared with the DSP I2C/SPI
After filtering the oversampled MPX signal, the RDS/RDBS demodulator extracts the RDS Data Clock, RDS
Data signal and the Quality information.
The following RDS/RBDS decoder synchronizes the bitwise RDS stream to a group and block wise information.
This processing also includes error detection and error correction algorithms.
In addition, an automatic flywheel control avoids exhausting data exchange between RDS/RDBS processor and
the host.
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