APPLICATION
2.2 Timer
RESET
q X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
TAM
TACON
CONAL
CONAH
TAL
TAH
ICON1
(address 3016)
(address 3116)
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
(address 3E16)
110001102
XXXXX0002
7716
0016
9 F1 6
0016
XXX0XXX02
CLI
TAM (address 3016), bit 6 0
•All interrupts disabled
•Timer A: IGBT output mode
•Noise filter: f(XIN); External trigger delayed: No delay
[ •Setting compare register value “H” width 5 µs
]
•Setting timer A count value
Cycle 20 µs setting
•Timer A, INT0 interrupt: Disabled
•Interrupts enabled
•Timer A count start
009F16
007716
000016
P50/TAOUT
Timer A start Match with
compare
register
Timer A
underflow
Input from
INT0 pin
Fig. 2.2.28 Control procedure
2-30
38C3 Group User’s Manual