APPLICATION
2.2 Timer
2.2.4 Notes on timer A (PWM mode and IGBT output mode)
(1) When timer starts first or last value of compare register is “000016”
After “L” level (timer A output active edge switch bit is “0”; when starting from “L” output) is output
during 2 cycles (until timer underflows two times), PWM output or IGBT output starts.
Reason: When data is written to timer A and compare register, value of timer A and value of
compare register are renewed at timer underflow. In case of this, compare register value
and timer value are compared before renewal, so that they are judged to be equal, and
TAOUT output becomes “L”. (Timer A output active edge switch bit = “0”: when starting from
“L” output)
Timer A underflow should cause “H” output, but the match have the priority. (see “Figure
2.2.29”)
Compare register value is
“000016”
(last value or initial value)
Compare register value is value which is written at
Timer A start
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.29 PWM output and IGBT output (1)
Timer A underflow
Timer A underflow
(2) When compare register is set to “000016” (last value is except “000016”)
Next 1 cycle of the cycle in which data is written to timer A and compare register is output “H”, and
“L” is output from the next cycle. (timer A output active edge switch bit = “0”: when starting from “L”
output)
(see “Figure 2.2.30”)
Compare register value is
last value
Compare register value is “000016”
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.30 PWM output and IGBT output (2)
Timer A underflow
Timer A underflow
38C3 Group User’s Manual
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