PIC16F636T-I/SL(2005) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F636T-I/SL
(Rev.:2005)
(Rev.:2005)
Microchip Technology
PIC16F636T-I/SL Datasheet PDF : 196 Pages
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PIC12F635/PIC16F636/639
REGISTER 11-6: CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUTOCHSEL AGCSIG MODMIN1 MODMIN0 LCZSEN3 LCZSEN2
bit 8
R/W-0
LCZSEN1
R/W-0
LCZSEN0
R/W-0
R5PAR
bit 0
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
AUTOCHSEL: Auto Channel Select bit
1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TSTAB; or otherwise, blocks the
channel(s).
0 = Disabled – AFE follows channel enable/disable bits defined in Register 0
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set
when the AGC begins regulating.
0 = Disabled – the AFE passes signal of any level it is capable of detecting
MODMIN<1:0>: Minimum Modulation Depth bit
00 = 50%
01 = 75%
10 = 25%
11 = 12%
LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit
0000 = -0dB (Default)
:
1111 = -30dB
R5PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Note 1: Assured monotonic increment (or decrement) by design.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 11-7: COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COLPAR7 COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2
bit 8
R/W-0
COLPAR1
R/W-0
COLPAR0
R/W-0
R6PAR
bit 0
bit 8
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the config register row parity bits contain an odd number of
set bits.
bit 7
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in config registers 0 through 5 contain an odd
number of set bits.
bit 6
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in config registers 0 through 5 contain an odd
number of set bits.
bit 5
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in config registers 0 through 5 contain an odd
number of set bits.
bit 4
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in config registers 0 through 5 contain an odd
number of set bits.
bit 3
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in config registers 0 through 5 contain an odd
number of set bits.
bit 2
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in config registers 0 through 5 contain an odd
number of set bits.
bit 1
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in config registers 0 through 5 contain an odd
number of set bits.
bit 0
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41232B-page 108
Preliminary
© 2005 Microchip Technology Inc.
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