ST24LC21M1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST24LC21M1TR Datasheet PDF : 18 Pages
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ST24LC21
Figure 10. Write Modes Sequence
VCLK
BYTE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
VCLK
PAGE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
R/W
ACK
ACK
DATA IN N
AI01504B
Read Operations
On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 12. This is followed by another
START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master does NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
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