ST24LC21M1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST24LC21M1TR Datasheet PDF : 18 Pages
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Figure 11. Inhibited Write when VCLK = 0
ST24LC21
VCLK
BYTE WRITE
PAGE WRITE
CONTROL
BYTE
ACK
ACK
WORD ADDR
DATA
ACK
CONTROL
BYTE
ACK
ACK
ACK
ACK
WORD ADD n
DATA n
DATA n + 1 DATA n + 7
ACK
AI01505
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24LC21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24LC21 terminate the
data transfer and switches to a standby state.
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