MACH221SP-7VC View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
MACH221SP-7VC Datasheet PDF : 48 Pages
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MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-6
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial
Output
6
7.5
10
12
14
15
18 ns
tS
Setup Time from Input, I/O, or Feedback D-type 5
5.5
to Clock
T-type 5.5
6.5
6.5
7.5
7
8.5
10
12
ns
8
10
11
13.5
ns
tH
Register Data Hold Time
0
0
0
0
0
0
0
ns
tCO
Clock to Output
4
4.5
6
8
10
10
12 ns
tWL
Clock Width
tWH
LOW 2.5
3
5
6
6
6
7.5
ns
HIGH 2.5
3
5
6
6
6
7.5
ns
External
D-type 111
100
Feedback 1/(tS + tCO) T-type 105
91
fMAX
Maximum
Frequency Internal Feedback (fCNT)
D-type 166
T-type 150
133
125
80
66.7
54
50
42
MHz
74
62.5
50
47.6
39
MHz
100
83.3
69
66.6
55.6
MHz
91
76.9
62.5
62.5
51.3
MHz
No Feedback 1/(tWL + tWH)
200
167
100
83.3
83.3
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate 5
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0
0
0
0
0
0
ns
tGO
Gate to Output
7
7
13
7
7.5
8
10
11
11
(note 6) ns
(note 4)
(note 5)
13.5
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
2.5
3
5
6
6
6
7.5
ns
20
9
9.5
12
14
17
17
(note 6) ns
20.5
tSIR
Input Register Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIR
Input Register Hold Time
1.5
2
2
2
2.5
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
20
10
11
13
15
18
18
(note 6) ns
22
tICS
Input Register Clock to Output Register D-type 8
Setup
T-type 9
9
10
10
11
12
14.5
15
18
ns
13
16
16
19.5
ns
tWICL
tWICH
Input Register
Clock Width
LOW 2.5
3
HIGH 2.5
3
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
200
167
5
6
6
6
7.5
ns
5
6
6
6
7.5
ns
100
83.3
83.3
83.3
66.7
MHz
tSIL
Input Latch Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIL
Input Latch Hold Time
1.5
2
2
2
2.5
2.5
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
12
14
17
20
20
24 ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
13
14
16
19
22
22
26.5 ns
tSLL
Setup Time from Input, I/O, or Feedback Through 7
Transparent Input Latch to Output Latch Gate
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
tWIGL
Input Latch Gate Width LOW
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
9
10
2.5
3
11
13
16
16
19.5
ns
5
6
6
6
7.5
ns
12
12.5
14
16
19
19
23 ns
MACH 1 & 2 Families
27
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