Table A-7 Background Debugging Mode Timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol Min
Max
Unit
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
B6 CLKOUT High to FREEZE Asserted/Negated
B7 CLKOUT High to IFETCH High Impedance
B8 CLKOUT High to IFETCH Valid
B9 DSCLK Low Time
B10 FREEZE Asserted to IFETCH Valid
tDSISU
15
—
ns
tDSIH
10
—
ns
tDSCSU
15
—
ns
tDSCH
10
—
ns
tDSOD
—
25
ns
tDSCCYC
2
—
tcyc
tFRZAN
—
50
ns
tIFZ
—
50
ns
tIF
—
50
ns
tDSCLO
1
—
tcyc
tFRZIF
TBD
—
tcyc
A
Notes:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
MOTOROLA
A-20
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL