SPAKMC331MFC20 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
SPAKMC331MFC20 Datasheet PDF : 254 Pages
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A
Table A-9 QSPI Timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, 200 pF load on all QSPI pins)
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop
DC
DC
1/4
System Clock Frequency
1/4
System Clock Frequency
1 Cycle Time
Master
Slave
2 Enable Lead Time
Master
Slave
3 Enable Lag Time
Master
Slave
4 Clock (SCK) High or Low Time
Master
Slave2
5 Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
6 Data Setup Time (Inputs)
Master
Slave
tqcyc
tlead
tlag
tsw
ttd
tsu
4
510
4
—
2
128
2
—
—
1/2
2
—
2 tcyc – 60
2 tcyc – n
17
13
255 tcyc
—
8192
—
30
—
20
—
tcyc
tcyc
tcyc
tcyc
SCK
tcyc
ns
ns
tcyc
tcyc
ns
ns
7 Data Hold Time (Inputs)
Master
Slave
thi
0
—
ns
20
—
ns
8 Slave Access Time
ta
—
1
tcyc
9 Slave MISO Disable Time
tdis
—
2
tcyc
10 Data Valid (after SCK Edge)
Master
tv
—
50
ns
Slave
—
50
ns
11 Data Hold Time (Outputs)
Master
Slave
tho
0
—
ns
0
—
ns
12 Rise Time
Input3
Output
13 Fall Time
Input3
Output
tri
—
2
µs
tro
—
30
ns
tfi
—
2
µs
tfo
—
30
ns
Notes:
1 All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources
are at valid VOH/VOL prior to SCK transitioning between valid VOL and VOH. Due to process variation, logic decision
point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
MOTOROLA
A-24
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
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