4
SYNCR Y field determines the count modulus for a modulo 64 down counter, causing
it to divide by a value of Y + 1. When W or Y values change, VCO frequency changes,
and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit that
is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is en-
abled, and system clock frequency is one-fourth VCO frequency; setting X disables
the divider, doubling clock speed without changing VCO speed. There is no relock de-
lay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
FSYSTEM = FREFERENCE[4(Y + 1)(22W + X) ]
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by
the W, X, and Y bits must be within the limits specified for the MCU. Do not use a com-
bination of bit values that selects either an operating frequency or a VCO frequency
greater than the maximum specified values in APPENDIX A ELECTRICAL CHARAC-
TERISTICS.
Table 4-7 shows clock control multipliers for all possible combinations of SYNCR bits.
Table 4-8 shows clock frequencies available with a 32.768-kHz reference and a max-
imum specified clock frequency of 20.97 MHz.
Table 4-7 Clock Control Multipliers
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus
Y
000000
000001
000010
011111
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
[W:X] = 00
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
Prescalers
[W:X] = 01
[W:X] = 10
8
16
16
32
24
48
32
64
40
80
48
96
56
112
64
128
72
144
80
160
88
176
96
192
104
208
112
224
120
240
128
256
136
272
144
288
152
304
160
320
168
336
[W:X] = 11
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
MOTOROLA
4-12
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL