TDA9111 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA9111 Datasheet PDF : 43 Pages
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TDA9111
Figure 9.
PLL1F
7
(Loop Filter)
(1.4V<V7<6.4V)
I0
I0
2
6
4 I0
R0
6.4V
1.6V
RS
FLIP FLOP
5
6.4V
C0
1.6V
0 0.875THTH
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current propor-
tional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6 V and 6.4 V.
The control voltage of the VCO is between 1.4 V
and 6.4 V (see Figure 9). The theoretical frequen-
cy range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value.
The sync frequency must always be higher than
the free running frequency. For example, when us-
ing a sync range between 25 kHz and 100 kHz,
the suggested free running frequency is 22 kHz.
PLL1 ensures the coincidence between the lead-
ing edge of the sync signal and a phase reference
REF1 obtained by comparison between the saw-
tooth of the VCO and an internal DC voltage Vb.
Vb is I2C adjustable between 2.9 V and 4.2 V (cor-
responding to ±10 %) (see Figure 10).
The TDA9111 also includes a Lock/Unlock identi-
fication block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal. This information is available through
I2C, and also on pin 3 if HLock/Unlock option has
been set through Subaddress 02,D8.
Figure 10. PLL1 Timing Diagram
H O SC
Sawtooth 7/8 TH
REF1
HSync
1/8 TH
6.4V
Ref. for H Position
Vb
(2.9V<Vb<4.2V)
1.6V
Phase REF1 is obtained by comparison between
the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.
The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A ±10% TH phase
adjustment is possible around the 3.5V point.
26/43
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