MC9S08SH8CSC View Datasheet(PDF) - Freescale Semiconductor
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MC9S08SH8CSC Datasheet PDF : 341 Pages
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Chapter 17 Development Support
Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
R-C RISE
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
272
Freescale Semiconductor
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