AD8260ACPZ-RL(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8260ACPZ-RL
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD8260ACPZ-RL Datasheet PDF : 32 Pages
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Parameter
ACCURACY
Absolute Gain Error
Gain Law Conformance (DNL)
GAIN CONTROL
Gain Step per Code
Gain Range
Response Time
LOGIC INTERFACES
High Level Input Voltage
Low Level Input Voltage
Logic Input Bias Current
POWER SUPPLY
Supply Voltage
Quiescent Current
PSRR
Power Dissipation
ENABLE TIMES
Chip Enable Time
Preamplifier and DGA Enable Time
Driver Enable Time
DISABLE TIMES
Chip Disable Time
Preamplifier and DGA Disable Time
Driver Disable Time
Conditions
Min Typ
All gain codes, limits are 3σ
Differential gain error code-to-code
−0.5 ±0.15
−0.3 ±0.15
3.0
Default = −6dB to +24 dB
30
30 dB gain change (gain code stepped from 0001 to 1011)
50
Logic high, VLOGIC = 3.3 V
Logic low
1.4
0
0.2
18
Single supply
Dual supply
Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001)
TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on
TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off
Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000)
VS = ±5 V, no signal
Max gain (gain code = 1011), gain = 24 dB, 1 MHz
Driver amplifier, 1 MHz
No signal
No signal, VPOS − VNEG = 10 V
3.3
±3.3
28.3
19.1
10.8
35
34.2
−30
−48
93
342
Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1
0.4
All at once, TXEN = 0 to 1, gain code = 0000 to 0001,
0.3
ENBL = 0 to 1
ENBL = 1, TXEN = 0, gain code = 0000 to 0001
0.3
ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1
0.2
TXEN = 1 to 0, gain code = 0001 to 0000,
20
ENBL = 1 to 0, ISUPPLY = 100 μA
All at once, TXEN = 1 to 0, gain code = 0001 to 0000,
50
ENBL = 1 to 0, ISUPPLY = 35 μA
ENBL = 1, TXEN = 0, gain code = 0001 to 0000
0.4
ENBL = 1, gain code = 0000, TXEN = 1 to 0
2.2
AD8260
Max Unit
+0.5 dB
+0.3 dB
dB
dB
ns
VS
V
0.8 V
μA
nA
10 V
±5 V
mA
mA
mA
μA
mA
dB
dB
mW
mW
μs
μs
μs
μs
μs
μs
μs
μs
Rev. 0 | Page 5 of 32
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