TS68230 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TS68230 Datasheet PDF : 61 Pages
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TS68230
Programmable Options Mode 0 - Port A Submode 01 and Port B Submode 01
PACR
76
01
Port A Submode
Submode 01
PACR
543
0XX
100
101
110
111
H2 Control
Input pin - edge-sensitive status inputs, H2S is set on an asserted edge.
Output pin - negated, H2S is always clear.
Output pin - asserted, H2S is always clear.
Output pin - interlocked input handshake protocol, H2S is always clear.
Output pin - pulsed input handshake protocol, H2S is always clear.
PACR
2
0
1
H2 Interrupt Enable
The H2 interrupt is disabled.
The H2 interrupt is enabled.
PACR
1
0
1
H1 SVCRQ Enable
The H1 interrupt and DMA request are disabled.
The H1 interrupt and DMA request are enabled.
PACR
0
0
1
H1 Status Control
The H1S status bit is set when either the port A initial or final output latch can accept new data
It is clear when both latches are full and cannot accept new data.
The H1S status bit is one when both of the port A output latches are empty. It is clear when at
least one latch is full.
PBCR
76
01
Port B Submode
Submode 01
PBCR
543
0XX
100
101
110
111
H4 Control
Input pin - edge-sensitive status input, H4S is set on an asserted edge.
Output pin - negated, H4S is always cleared.
Output pin - asserted, H4S is always cleared.
Output pin - interlocked input handshake protocol, H4S is always cleared.
Output pin - pulsed input handshake protocol, H4S is always cleared.
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