PSD834F3A-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F3A-12UI Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
Table 49.
Symbol
CPLD combinatorial timing (3 V devices) (continued)
Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
tARPW
CPLD register clear
or preset pulse width
25
30
35
+ 20
ns
tARD
CPLD array delay
Any
macrocell
25
29
33 + 4
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Figure 40. Synchronous clock mode timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
Fast
PT
Turbo Slew
rate
Unit
Aloc off
(1)
Maximum
frequency
External
feedback
1/(tS+tCO)
40.0
30.30
25.00
MHz
fMAX
tS
tH
tCH
tCL
tCO
Maximum
frequency
Internal
feedback (fCNT)
Maximum
frequency
Pipelined data
1/(tS+tCO–10)
1/(tCH+tCL)
66.6
83.3
43.48
50.00
31.25
35.71
Input setup time
12
15
20
+2
Input hold time
0
0
0
Clock high time Clock input 6
10
15
Clock low time Clock input 6
10
15
Clock to output
delay
Clock input
13
18
22
+ 10
MHz
MHz
ns
ns
ns
ns
– 2 ns
Doc ID 7833 Rev 7
101/128
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