PSD854F3A-15UI View Datasheet(PDF) - STMicroelectronics
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Description
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PSD854F3A-15UI Datasheet PDF : 128 Pages
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I/O ports
PSD8XXFX
16.10
Port configuration registers (PCR)
Each port has a set of port configuration registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in Table 8. The addresses in Table 8 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three port
configuration registers (PCR), shown in Table 23, are used for setting the port
configurations. The default Power-up state for each register in Table 23 is 00h.
16.11
Control register
Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode,
and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only ports A and B
have an associated Control register.
16.12
Direction register
The Direction register, in conjunction with the output enable (except for port D), controls the
direction of data flow in the I/O ports. Any bit set to '1' in the Direction register causes the
corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default
mode for all port pins is input.
Figure 27 and Figure 28 show the port architecture diagrams for ports A/B and C,
respectively. The direction of data flow for ports A, B, and C are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction register has sole control of a given
pin’s direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 26. Since port D only contains three pins
(shown in Figure 30), the Direction register for port D has only the three least significant bits
active.
16.13
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a ’1.’ The default pin drive is CMOS.
Note that the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates in a high slew rate when the corresponding bit in the Drive register is set to ’1.’ The
default rate is slow slew.
Table 27 shows the Drive register for ports A, B, C, and D. It summarizes which pins can be
configured as Open Drain outputs and which pins the slew rate can be set for.
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Doc ID 7833 Rev 7
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