PSD854F3A-15UI View Datasheet(PDF) - STMicroelectronics
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Description
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PSD854F3A-15UI Datasheet PDF : 128 Pages
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Power management
PSD8XXFX
17.1
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes high, and the PSD enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
● If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operating mode. The PSD also returns to normal operating mode if either PSD Chip
Select input (CSI, PD2) is low or the Reset (RESET) input is high.
● The MCU address/data bus is blocked from all memory and PLDs.
● Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from
the PLDs does not block CLKIN (PD1) from the APD Unit.
● All PSD memories enter Standby mode and are drawing standby current. However, the
PLD and I/O ports blocks do not go into Standby mode because you don’t want to have
to wait for the logic and I/O to “wake up” before their outputs can change. See Table 29
for Power-down mode effects on PSD ports.
● Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
Table 29. Power-down mode’s effect on ports
Port function
MCU I/O
PLD Out
Address Out
Data port
Peripheral I/O
No change
No change
Undefined
Tri-state
Tri-state
Pin level
80/128
Doc ID 7833 Rev 7
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