M48T128VPM(2010) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T128VPM
(Rev.:2010)

5.0 or 3.3 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T128Y, M48T128V

Operation modes

2.2

WRITE mode

The M48T128Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)

are low state after the address inputs are stable.

The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE

is terminated by the earlier rising edge of W or E. The addresses must be held valid

throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or

tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in

must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G

should be kept high during WRITE cycles to avoid bus contention; although, if the output bus

has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W

falls.

Figure 5. WRITE enable controlled, WRITE AC waveform

A0-A16

E

W

DQ0-DQ7

tAVEL

tAVAV

VALID

tAVWH

tWHAX

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI02382

Figure 6. Chip enable controlled, WRITE AC waveforms

A0-A16

E

W

DQ0-DQ7

tAVEL

tAVWL

tAVAV

VALID

tAVEH

tELEH

tEHAX

tEHDX

DATA INPUT

tDVEH

AI02383

Doc ID 5746 Rev 6

9/23

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