ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

2

Pinout and pin description

Pinout and pin description

AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the

beginning of each memory cycle. The rising edge of AS indicates that address, Read/Write

(RW), and Data signals are valid for memory transfers.

DS. Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data

movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid

at the leading edge of DS. During a read cycle, Data In must be valid prior to the trailing

edge of DS. When the ST9 accesses on-chip memory, DS is held high during the whole

memory cycle.

RESET. Reset (input, active low). The ST9 is initialized by the Reset signal. With the

deactivation of RESET, program execution begins from the Program memory location

pointed to by the vector contained in program memory locations 00h and 01h.

RW. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for

external memory transactions. RW is low when writing to external memory, and high for all

other transactions.

OSCIN, OSCOUT. Oscillator (input and output). These pins connect a parallel-resonant

crystal, or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of

the oscillator inverter; OSCOUT is the output of the oscillator inverter.

HW0SW1. When connected to VDD through a 1K pull-up resistor, the software watchdog

option is selected. When connected to VSS through a 1K pull-down resistor, the hardware

watchdog option is selected.

VPWO. This pin is the output line of the J1850 peripheral (JBLPD). It is available only on

some devices.

RX1/WKUP6. Receive Data input of CAN1 and Wake-up line 6. Available only on some

devices. When the CAN1 peripheral is disabled, a pull-up resistor is connected internally to

this pin.

TX1. Transmit Data output of CAN1. Available on some devices.

P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or CMOS compatible). 11 lines (64-pin

devices) or 22 lines (100-pin devices) providing the external memory interface for

addressing 2K or 4M bytes of external memory.

P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4.[7:4], P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines

(Input/Output, TTL or CMOS compatible). I/O lines grouped into I/O ports of 8 bits, bit

programmable under software control as general purpose I/O or as alternate functions.

P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0] Additional I/O Port Lines available on 100-

pin versions only.

P3.0, P6[7:6] Additional I/O Port Lines available on ST92F250 version only.

AVDD. Analog VDD of the Analog to Digital Converter (common for ADC 0 and ADC 1).

AVDD can be switched off when the ADC is not in use.

AVSS. Analog VSS of the Analog to Digital Converter (common for ADC 0 and ADC 1).

VDD. Main Power Supply Voltage. Four pins are available on 100-pin versions, two on 64-pin

versions. The pins are internally connected.

Doc ID 8848 Rev 7

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