CY8CPLC20-OCD(2009) View Datasheet(PDF) - Cypress Semiconductor
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Description
Manufacturer
CY8CPLC20-OCD Datasheet PDF : 44 Pages
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CY8CPLC20
14. Document History Page
Document Title: CY8CPLC20 Powerline Communication Solution
Document Number: 001-48325
Rev. ECN No.
Orig. of Submission
Change
Date
Description of Change
** 2571957 GHH/PYRS 09/24/08 New Datasheet
*A 2731927 GHH/HMT/ 07/06/09 Added
DSG
- Configurable baud rates and FSK frequencies
- PLC Pod Kits for development purposes
Modified
- Pin information for all packages
*B 2748537
GHH
See ECN
Added Sections on ‘Getting Started’ and ‘Document Conventions’
Modified the following Electrical Parameters
- FIMO6 Min: Changed from 5.75 MHz to 5.5 MHz
- FIMO6 Max: Changed from 6.35 MHz to 6.5 MHz
- SPIS (Maximum input clock frequency): Changed from 4.1 ns to 4.1 MHz
- TWRITE (Flash Block Write Time): Changed from 40 ms to 10 ms
*C 2752799
GHH
08/17/09 Posting to external web.
*D 2759000
GHH
09/02/2009 Fixed typos in the data sheet
*E 2778970
FRE
10/05/2009
Added a table for DC POR and LVD Specifications
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
- Modified FIMO6, TWRITE, and Power Up IMO to Switch specifications
- Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, and
SRPOWER_UP specifications
Added 48-Pin QFN (Sawn) package diagram and CY8CPLC20-48LTXI and
CY8CPLC20-48LTXIT part details in the Ordering Information table
Updated section 4 and Tables 9-1, 9-2, and 9-3 to state the requirement to use
the external crystal for PLC protocol timing
Table 9-1 and Figure 9-1: Changed pins 9 and 25 from NC to RSVD
Table 9-2 and Figure 9-2: Changed pins 7 and 39 from NC to RSVD
Table 9-3 and Figure 9-3: Changed pins 14 and 77 from NC to RSVD
Tables 9-1, 9-2, 9-3: Added explanation to Connect a 0.1 uF capacitor between
XTAL_Stability and VSS.
Fixed minor typos.
Document Number: 001-48325 Rev. *E
Page 43 of 44
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