ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLITE39F2U6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read / Write

Reset Value: 0110 0xx0 (6xh)

7

0

0

CR1 CR0

WDG

RF

LOCKED LVDRF AVDF AVDIE

Bit 1 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit is set. Refer to Figure

19 and to Section 7.6.2.1 for additional details.

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

register must be written immediately after reset to

adjust the RC oscillator frequency and to obtain an

accuracy of 1%. Refer to section 7.3 on page 24

Bit 4 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software (by

reading SICSR register) or an LVD Reset (to en-

sure a stable cleared state of the WDGRF flag

when CPU starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

RESET Sources

External RESET pin

Watchdog

LVD

LVDRF

0

0

1

WDGRF

0

1

X

Bit 0 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag is

set. The pending interrupt information is automati-

cally cleared when software enters the AVD inter-

rupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

Bit 3 = LOCKED PLL Locked Flag

This bit is set by hardware. It is cleared only by a

power-on reset. It is set automatically when the

PLL reaches its operating frequency.

0: PLL not locked

1: PLL locked

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (by reading). When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

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