ST7LITE3xF2
INTERRUPTS (cont’d)
Figure 20. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
FETCH NEXT INSTRUCTION
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
RESET Reset
TRAP Software Interrupt
0
AWU 7 Interrupt
N/A
Highest
AWUCSR Priority
1
ei0
External Interrupt 0
2
ei1
External Interrupt 1
N/A
3
ei2
External Interrupt 2
4
ei3
External Interrupt 3
5 LITE TIMER LITE TIMER RTC2 interrupt
LTCSR2
6
LINSCI LINSCI Interrupt
SCICR1/
SCICR2
7
SI
AVD interrupt
SICSR
8
AT TIMER Output Compare Interrupt
AT TIMER or Input Capture Interrupt
PWMxCSR
or ATCSR
9
AT TIMER Overflow Interrupt
ATCSR
10
LITE TIMER Input Capture Interrupt
LITE TIMER
11
LITE TIMER RTC1 Interrupt
12
SPI
SPI Peripheral Interrupts
LTCSR
LTCSR
SPICSR
Lowest
Priority
13 AT TIMER AT TIMER Overflow Interrupt 2
ATCSR2
Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
Note 2: These interrupts exit the MCU from “ACTIVE-HALT” mode only.
yes
no
yes1)
yes
no
no
no
no
yes2)
no
yes2)
yes
no
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
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