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ST7PLITE35F2M6TR View Datasheet(PDF) - STMicroelectronics

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ST7PLITE35F2M6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
– At the second input capture on the falling edge of
the pulse, we assume that the values in the reg-
isters are as follows:
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
Now pulse width P between first capture and sec-
ond capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec-
imal (ATICR2 - ATICR1 – 1) * 1ms
Figure 45. Long Range Input Capture Timing Diagram
fOSC/32
TB Counter1 F9h 00h LT1
F9h 00h _ _ _ _ _ _ _ _ _ LT2 _ _ _ _ _ _
CNTR1
___
ATH1 & ATL1
___
ATH2 & ATL2
LTIC
LTICR
00h
LT1
LT2
ATICRH
0h
ATH1
ATH2
ATICRL
00h
ATL1
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
11.2.4 Low Power Modes
Mode Description
SLOW The input frequency is divided by 32
WAIT No effect on AT timer
ACTIVE- AT timer halted except if CK0=1,
HALT CK1=0 and OVFIE=1
HALT AT timer halted.
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