FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
7.0
7.1
7.2
Document Revision Information
The following tables list the changes made to the FM2112 Datasheet
resulting in the publication of a new revision.
Nomenclature
Document revisions are placed in either of two categories to allow the
user to quickly focus on changes of a substantive nature (Category 1),
that is, changes that may have an impact on system or board level
design.
Category 1 changes describe documentation revisions that reflect
substantial changes in the way the form, fit or function of the device is
described. These changes may affect the design of a product using the
device. An example might be the correction of a wrong pin number
assignment because that would affect the trace routing on a board.
Category 2 changes are documentation changes consisting of
clarifications or corrections, primarily to descriptive or graphical
sections, and do not represent substantial changes in the descriptions
of form, fit or function. Typo's and grammatical error corrections are
not recorded in the table below.
Rev 1.0 to 1.1 Changes
Page
Category
1
2
Description
1
46
2
113
3
74
4
85
5
23
6
144
7
129
8
129
9
151
10
149
11
72
12
111
17
106
18
113
X
Removed references to a switch priority protected from the PWD
mechanism. Also noted in QUEUE_CFG_1 register.
X
Added note of clarification to Table 108.
X
Figure 22: Removed reference to DS_N pin, which does not exist.
X
Table 41: Added version number for A5 silicon.
X
Table 1: Corrected RCK to port assignments for the 4 port groups
X
Table 179. Corrected RCK to port assignments for the 4 port groups.
X
Table 144: Recommend setting “Ignore IFG errors” and “Ignore preamble”
errors bits.
X
Table 144: Change bits 3:0 from reserved to LF, controlling the /K/A/R
randomization.
X
Added note on power supply sequencing
X
Table 185: Changed TESTMODE pin from “leave unconnected” to “pull
down”.
X
Table 23: Add note on overshoot for VIH on LVTTL inputs.
X
Table 100: QUEUE_CFG_1, TX shared watermark. Remove text to the
effect that switch priority 15 is exempt from PWD dropping
X
Table 90: Include new definitions of 3 bits in TRUNK_HASH_MASK table.
X
Table 104: Documented QUEUE_CFG_5 register, which had been missing.
163
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