Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
Note:
3.2.5.2
3.2.5.3
3.2.5.4
3.2.6
• GARP - Both GMRP and GVRP: 0x0180C2000020-1
• IGMP v3: 0x01005E000001
• All other IEEE: 0x0180C20000xy: where x=0 & y > 3, x=1, or x=2 & y > 1.
Broadcast is also sent to the CPU, however it is not a trap.
When a frame is trapped, it is sent to the CPU instead of being treated
as a general multicast address. The hardware uses a special internal
priority for this transfer, and that prevents the frames from being
dropped for PWD calculations, except in the case where the entire
memory would fill up.
CPU MAC Address
In parallel with the MAC address lookup and the protocol multicast
address traps, there is a programmable register on which a lookup is
performed every cycle. If the destination address matches this register
then the frame is sent to the CPU port irrespective of VLAN. However,
source address lookups for security and triggers still apply. Ingress
rules apply to the frame, but Egress rules do not.
Ether-type Trap
There is also a configurable Ether-type trap. Any frame that matches
the Ether-type will be trapped, and not forwarded normally.
Multicast Groups
Any entry in the MAC address table may be a multicast group.
Therefore, there may be up to 16k multicast entries. Flooding may be
used to forward any multicast group for which there is no entry
configured in the MAC address table.
MAC Address Table and VLAN Table
{Described in registers Table 79, Table 84, and Table 85}
The Intel®Ethernet Switch Family supports a 16k-entry MAC address
table. Any of the 16k entries may be a unicast or a multicast address.
The table is an 8-way set-associative hash table.
The table has the following fields:
• MAC Address
• FID: Learning group; for multiple spanning trees this is equal to the VLAN-ID, for
shared spanning trees it is equal to zero.
• Valid: Entry is valid
• Lock: Manager has specified this address and switch may not age it out.
• Age: Age time stamp
• Parity
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