Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
Table 2-10. Supported Output Standards4
Output Standard
Single-ended Interfaces
LVTTL/D1
LVCMOS33/D1
LVCMOS25/D1, 2
LVCMOS18/D1, 2
LVCMOS15/D1, 2
LVCMOS12/D1, 2
PCIX15
PCI33, PCIX33, AGP1X33,
AGP2X33
HSTL18_I
Drive
8mA, 16mA, 24mA
8mA, 16mA, 24mA
4mA, 8mA, 12mA, 16mA,
4mA, 8mA, 12mA, 16mA,
4mA, 8mA, 12mA, 16mA,
2mA, 4mA, 8mA, 12mA
N/A
N/A
N/A
VCCIO (Nom)
3.3
3.3
2.5
1.8
1.5
1.2
1.5
3.3
1.8
HSTL18_II
N/A
1.8
HSTL15_I
N/A
1.5
HSTL15_II
N/A
1.5
SSTL33_I
SSTL33_II
SSTL25_I
N/A
3.3
N/A
3.3
N/A
2.5
SSTL25_II
N/A
2.5
SSTL18_ I
N/A
1.8
SSTL18_II
N/A
1.8
Differential Interfaces
SSTL18D_I
N/A
1.8
SSTL25D_I
N/A
2.5
SSTL18D_II, SSTL25D_II
N/A
1.2/2.5/3.3
SSTL33D_I, II
N/A
HSTL15D_I, HSTL18D_I
N/A
3.3
1.5/1.8
HST15D_II, HSTL18D_II
N/A
1.5/1.8
LVDS
2mA, 3.5mA, 4mA, 6mA
N/A
Mini-LVDS
3.5mA, 4mA, 6mA
N/A
BLVDS25
N/A
N/A
MLVDS25
N/A
N/A
LVPECL333
N/A
3.3
HYPT (Hyper Transport)
3.5mA, 4mA, 6mA
N/A
RSDS
2mA, 3.5mA, 4mA, 6mA
N/A
1. D refers to open drain capability.
2. User can select either drive current or driver impedances but not both.
3. Emulated with external resistors.
4. No GTL or GTL+ support.
On-chip Output Termination
None.
None
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None
None
None, series: 50
None, series: 25, series + parallel to VCCIO/2:
25 + 60
None, series: 50
None, series: 25, series + parallel to VCCIO/2:
25 + 60
None
None
None, series: 50
None, series: 33, series + parallel to VCCIO/2:
33+ 60
None, series: 33
None, series: 33, series + parallel to VCCIO/2:
33+ 60
None, series: 33
None, series: 50
None, series: 33, series + parallel to VCCIO/2:
33+ 60
None
None, series: 50
None, series: 25, series + parallel to VCCIO/2:
25 + 60
None
None
None
None
None
None
None
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