LFSC3GA80EP1-6FCN1704C View Datasheet(PDF) - Lattice Semiconductor
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LFSC3GA80EP1-6FCN1704C Datasheet PDF : 237 Pages
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Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs:
• Parallel to VCCIO or GND
• Parallel to VCCIO/2
• Parallel to VTT
Figure 2-28 shows the single ended input schemes that are supported. The nominal values of the termination resis-
tors are shown in Table 2-9.
Figure 2-28. Input Termination Schemes
Termination Type
Discrete Off-Chip Solution
Lattice On-Chip Solution
VCCIO or GND
VCCIO or GND
Parallel termination to
Zo
to VCCIO, or parallel to
Zo
GND receiving end
Zo
Zo
OFF-chip
ON-chip
OFF-chip
ON-chip
Parallel termination to
VCCIO/2 receiving end
Parallel termination to
VTT at receiving end
VCCIO2
Zo
Zo
OFF-chip
ON-chip
VTT
Zo
Zo
OFF-chip
ON-chip
VCCIO
2Zo
Zo
2Zo
GND
OFF-chip
ON-chip
VTT
Zo
Zo
OFF-chip
ON-chip
In many situations designers can chose whether to use Thevenin or parallel to VTT termination. The Thevenin
approach has the benefit of not requiring a termination voltage to be applied to the device. The parallel to VTT
approach consumes less power.
VTT Termination Resources
Each I/O bank, except bank 1, has a number of VTT pins that must be connected if VTT is used. Note VTT pins can
sink or source current and the power supply they are connected to must be able to handle the relatively high currents
associated with the termination circuits. Note: VTT is not available in all package styles.
On-chip parallel termination to VTT is supported at the receiving end only. On-chip parallel output termination to VTT is
not supported.
The VTT internal bus is also connected to the internal VCMT node. Thus in one bank designers can implement either
VTT termination or VCMT termination for differential inputs.
DDRII/RLDRAMII Termination Support
The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to VTT
be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required cir-
cuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet.
2-31
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