LFSC3GA25E-5FN900I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA25E-5FN900I Datasheet PDF : 237 Pages
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Lattice Semiconductor
EBR Memory Timing Diagrams
Figure 3-6. Read Mode
CLKA
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
CSA
WEA
ADA
DIA
DOA
A0
A1
tSU tH
D0
tACCESS
D1
tACCESS
Invalid Data
A0
tACCESS
A1
A0
tACCESS
D0
tACCESS
D1
D0
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
Figure 3-7. Read Mode with Input Registers Only
CLKA
CSA
WEA
ADA
DIA
DOA
A0
A1
tSU tH
D0
D1
Invalid Data
A0
A1
tACCESS
tACCESS
D0
D1
output is only updated during a read cycle
3-21
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