Lattice Semiconductor
Figure 3-8. Read Mode with Input and Output Registers
CLKA
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
CSA
WEA
ADA
DIA
A0
A1
tSU tH
D0
D1
A0
A1
A0
DOA
DOA (Registered)
Mem(n) data from previous read
DOA
D0
tACCESS
Mem(n) data from previous read
output is only updated during a read cycle
Figure 3-9. Write Through (SP Read/Write On Port A, Input Registers Only)
D1
D0
D0
tACCESS
D1
CLKA
CSA
WEA
ADA
DIA
DOA
A0
tSU tH
D0
tACCESS
Data from Prev Read
or Write
A1
D1
tACCESS
D0
Three consecutive writes to A0
A0
D2
D3
tACCESS
D1
D2
D4
tACCESS
D3
D4
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
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