ADP1752ACPZ-0.75R7 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADP1752ACPZ-0.75R7

0.8 A, Low VIN, Low Dropout Linear Regulator

Analog Devices 

ADP1752/ADP1753

Data Sheet

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP1752/ADP1753 are designed for operation with small,

space-saving ceramic capacitors, but they can function with most

commonly used capacitors as long as care is taken with the

effective series resistance (ESR) value. The ESR of the output

capacitor affects the stability of the LDO control loop. A mini-

mum of 3.3 µF capacitance with an ESR of 500 mΩ or less is

recommended to ensure the stability of the ADP1752/ADP1753.

Transient response to changes in load current is also affected by

output capacitance. Using a larger value of output capacitance

improves the transient response of the ADP1752/ADP1753 to

large changes in load current. Figure 33 and Figure 34 show the

transient responses for output capacitance values of 4.7 µF and

22 µF, respectively.

T

ILOAD

1mA TO 800mA LOAD STEP, 2V/µs, 500mA/DIV

1

VOUT

2

50mV/DIV

VIN = 3.6V, VOUT = 1.5V

CIN = COUT = 4.7µF

CH1 500mA Ω BW CH2 50mV BW M1µs A CH1 380mA

T 11.6%

Figure 33. Output Transient Response, COUT = 4.7 µF

T

ILOAD

Input Bypass Capacitor

Connecting a 4.7 µF capacitor from the VIN pin to GND reduces

the circuit sensitivity to printed circuit board (PCB) layout,

especially when long input traces or high source impedance

are encountered. If output capacitance greater than 4.7 µF is

required, it is recommended that the input capacitor be increased

to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP1752/ADP1753, as long as they meet the minimum

capacitance and maximum ESR requirements. Ceramic

capacitors are manufactured with a variety of dielectrics,

each with different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure

the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a

voltage rating of 6.3 V or 10 V are recommended. Y5V and

Z5U dielectrics are not recommended, due to their poor tempera-

ture and dc bias characteristics.

Figure 35 shows the capacitance vs. voltage bias characteristics

of an 0805 case, 4.7 µF, 10 V, X5R capacitor. The voltage stability

of a capacitor is strongly influenced by the capacitor size and

voltage rating. In general, a capacitor in a larger package or with

a higher voltage rating exhibits better stability. The temperature

variation of the X5R dielectric is about ±15% over the −40°C to

+85°C temperature range and is not a function of package size

or voltage rating.

5

MURATA P/N GRM219R61A475KE34

4

3

1mA TO 800mA LOAD STEP, 2V/µs, 500mA/DIV

1

2

VOUT

20mV/DIV

VIN = 3.6V, VOUT = 1.5V

CIN = COUT = 22µF

CH1 500mA Ω BW CH2 20mV BW M1µs A CH1 530mA

T 12.2%

Figure 34. Output Transient Response, COUT = 22 µF

2

1

0

0

2

4

6

8

10

VOLTAGE BIAS (V)

Figure 35. Capacitance vs. Voltage Bias Characteristics

Equation 3 can be used to determine the worst-case capacitance

accounting for capacitor variation over temperature, component

tolerance, and voltage.

CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

(3)

where:

CEFF is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

Rev. E | Page 14 of 20

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