STM32F051x4 STM32F051x6 STM32F051x8
Revision history
Date
28-Aug-2015
Table 76. Document revision history (continued)
Revision
Changes
Updated the following:
– DAC and power management feature descriptions in Features
– Table 2: STM32F051xx family device features and peripheral
count
– Section 3.5.1: Power supply schemes
– Figure 13: Power supply scheme
– Table 17: Voltage characteristics
– Table 20: General operating conditions: updated the footnote
for VIN parameter
– Table 28: Typical and maximum current consumption from the
VBAT supply
– Table 52: ADC characteristics
– Table 33: High-speed external user clock characteristics:
replaced VDD with VDDIOX
– Table 34: Low-speed external user clock characteristics:
replaced VDD with VDDIOX
– Table 37: HSI oscillator characteristics and Figure 19: HSI
oscillator accuracy characterization results for soldered parts
– Table 38: HSI14 oscillator characteristics: changed the min
value for ACCHSI14
– Table 41: Flash memory characteristics: changed the values
for tME and IDD in write mode
5
– Table 43: EMS characteristics: changed the value of VEFTB
– Table 45: ESD absolute maximum ratings
– Figure 10: STM32F051x8 memory map
– Figure 21: TC and TTa I/O input characteristics
– Figure 22: Five volt tolerant (FT and FTf) I/O input
characteristics
– Figure 23: I/O AC characteristics definition
– tSTART definition in Table 24: Embedded internal reference
voltage
– tSTAB characteristics in Table 52: ADC characteristics
– Table 56: Comparator characteristics: changed the
description and values for VSC, VDDA and VREFINT
parameters. Added Figure 28: Maximum VREFINT scaler
startup time from power down
– Table 57: TS characteristics: changed the min value for TS-
temp
– Table 58: VBAT monitoring characteristics: changed the min
value for TS-vbat and the typical value for R parameters
– Section 6.3.22: Communication interfaces: updated the
description and features in the subsection I2C interface
characteristics
– Table 64: I2S characteristics: updated the min values for data
input hold time (master and slave receiver)
DocID022265 Rev 7
119/122
121