AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation
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AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
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48.15.5 EMAC
48.15.5.1 Timing Conditions
Timings are given assuming a capacitance load on data and clock as defined in Table 48-42.
Table 48-42. Capacitance Load on Data, Clock Pads
Supply
3.3V
1.8V
Max
20 pF
20 pF
Corner
Min
0 pF
0 pF
48.15.5.2 Timing Constraints
The Ethernet controller satisfies the timings of the standards given in Table 48-43, Table 48-44 and Table 48-45.
Table 48-43. EMAC Signals Relative to EMDC
Symbol
Parameter
Min
Max
Unit
EMAC1
Setup for EMDIO from EMDC rising
13.5
–
ns
EMAC2
Hold for EMDIO from EMDC rising
10
–
ns
EMAC3
EMDIO toggling from EMDC falling
0 (1)
2 (1)
ns
Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EMDC falling
edge and the signal change. The Max access time is the time between the EMDC falling edge and the signal stabilization.
Figure 48-22 illustrates Min and Max accesses for EMAC3.
Figure 48-22. Min and Max Access Time of EMAC Output Signals
EMDC
EMDIO
EMAC1
EMAC2
EMAC4
EMAC5
48.15.5.3 MII Mode
EMAC3 max
EMAC3 min
Table 48-44.
Symbol
EMAC4
EMAC5
EMAC6
EMAC7
EMAC8
EMAC9
EMAC10
EMAC11
EMAC12
EMAC MII Specific Signals
Parameter
Setup for ECOL from ETXCK rising
Hold for ECOL from ETXCK rising
Setup for ECRS from ETXCK rising
Hold for ECRS from ETXCK rising
ETXER toggling from ETXCK rising
ETXEN toggling from ETXCK rising
ETX toggling from ETXCK rising
Setup for ERX from ERXCK
Hold for ERX from ERXCK
Min
Max
Unit
10
–
ns
10
–
ns
10
–
ns
10
–
ns
3
25
ns
4.7
25
ns
3
25
ns
10
–
ns
10
–
ns
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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