AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
| |||
53. Revision History
In the tables that follow, the most recent version appears first.
Table 53-1. SAM9G46 Datasheet Rev. 11028G Revision History
Date Changes
General formatting and editorial changes throughout
Section 1. “Block Diagram”
Figure 1-1 “SAM9G46 Block Diagram”: added label “Backup Section”
Section 4. “Power Considerations”
Added Section 4.2 “Power Sequence Requirements” (transferred content from Section 48.12 “Core Power Supply POR
Characteristics”)
Section 5. “Memories”
Section 5.2.2 “TCM Interface”: in first sentence, “can be allocated to two areas” corrected to “can be allocated to three
areas”
Section 5.3.1 “I/O Drive Selection”: “EBI_CSA register” corrected to “CCFG_EBICSA register”
Section 7. “Peripherals”
Section 7.4 “Peripheral Signals Multiplexing on I/O Lines”: below last paragraph, deleted sentence “To amend EMC,
programmable delay has been inserted on PIO lines able to run at high speed”
Section 8. “ARM926EJ-S Processor Overview”
Section 8.4.10 “Thumb Instruction Set Overview”: deleted sentence “Table 5 shows the Thumb instruction set, for further
details, see the ARM Technical Reference Manual”
Section 10. “Boot Strategies”
Deleted sentence “For optimization purpose, nothing else is done.”
Section 10.5.3.2 “USB Class”: removed reference to “Windows XP”
Section 13. “Real-time Clock (RTC)”
08-Dec-15 Section 13.2 “Embedded Characteristics”: deleted bullet “Control of alarm and update Time/Calendar Data In”
Table 13-1 “Register Mapping”: RTC_CALR offset value ‘0x01819819’ corrected to ‘0x01210720’
Section 18. “Bus Matrix (MATRIX)”
Removed reset value from register description sections in Section 18.7.6 “Chip Configuration User Interface” (reset values
provided in Table 18-7 “Register Mapping (Chip Configuration User Interface)”)
Section 19. “External Memories”
Table 19-4 “EBI Pins and External Static Devices Connections”:
- added footnote to pins BE0–BE3
- in last two rows, changed two instances of “NLB” to “NUB”
Section “CFCE1 and CFCE2 Signals”: updated content describing DBW field configuration
Added Figure 19-9 “NAND Flash Signal Multiplexing on EBI Pins”
Section 21. “DDR SDR SDRAM Controller (DDRSDRC)”
Section 21.1 “Description”: updated note at end of section
Added Section 21.2 “Embedded Characteristics”
Section 21.4: changed title from “Product Dependencies” to “Initialization Sequence”
Section 21.4.1 “SDR-SDRAM Initialization”: updated steps 2 and 10
Section 21.4.2 “Low-power DDR1-SDRAM Initialization”: updated steps 2 and 11; replaced step 12 with standard text
Section 21.4.3 “DDR2-SDRAM Initialization”: updated steps 2, 7, and 21
Figure 21-12 “Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Device”: in diagram, inserted additional
cycle (“Latency = 2” corrected to “Latency = 3”)
1260 SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
Share Link: 