8.4.9 New ARM Instruction Set
.
Table 8-3.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Branch and exchange to Java
BLX (1)
Branch, Link and exchange
SMLAxy
SMLAL
SMLAWy
Signed Multiply Accumulate 16 * 16 bit
Signed Multiply Accumulate Long
Signed Multiply Accumulate 32 * 16 bit
SMULxy Signed Multiply 16 * 16 bit
SMULWy
QADD
QDADD
QSUB
QDSUB
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Mnemonic
MRRC
MCR2
MCRR
CDP2
BKPT
PLD
STRD
STC2
LDRD
LDC2
CLZ
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data Processing
Breakpoint
Soft Preload, Memory prepare to load from
address
Store Double
Alternative Store from Coprocessor
Load Double
Alternative Load to Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
42 SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15