AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

11.4.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

 RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

 SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software

reset should be performed until the end of the current one. This bit is automatically cleared at the end of the

current software reset.

 NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK

rising edge.

 URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is

also detected on the Master Clock (MCK) rising edge (see Figure 11-9). If the User Reset is disabled

(URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit

triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.

Figure 11-9. Reset Controller Status and Interrupt

MCK

Peripheral Access

read

RSTC_SR

NRST

NRSTL

URSTS

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)

2 cycle

resynchronization

2 cycle

resynchronization

82 SAM9G46 Series [DATASHEET]

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

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