11.5.2 Reset Controller Status Register
Name:
RSTC_SR
Address: 0xFFFFFD04
Access: Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
SRCMP
NRSTL
15
14
13
12
11
10
9
8
–
–
–
–
–
RSTTYP
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
URSTS
• URSTS: User Reset Status
0: No high-to-low edge on NRST happened since the last read of RSTC_SR.
1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Reset Type
General Reset
Wake Up Reset
Watchdog Reset
Software Reset
User Reset
Comments
Both VDDCORE and VDDBU rising
VDDCORE rising
Watchdog fault occurred
Processor reset required by the software
NRST pin detected low
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0: No software command is being performed by the reset controller. The reset controller is ready for a software command.
1: A software reset command is being performed by the reset controller. The reset controller is busy.
SAM9G46 Series [DATASHEET]
85
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15