AT91SAM7S64C-AU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM7S64C-AU Datasheet PDF : 775 Pages
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24. Clock Generator
24.1 Overview
The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
• PLLCK is the output of the Divider and PLL block
The Clock Generator User Interface is embedded within the Power Management Controller one and is described in
Section 25.9. However, the Clock Generator registers are named CKGR_.
24.2
Slow Clock RC Oscillator
The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section “DC
Characteristics” of the product datasheet.
24.3 Main Oscillator
Figure 24-1 shows the Main Oscillator block diagram.
Figure 24-1. Main Oscillator Block Diagram
MOSCEN
XIN
XOUT
Main
Oscillator
MAINCK
Main Clock
SLCK
Slow Clock
OSCOUNT
Main
Oscillator
Counter
Main Clock
Frequency
Counter
MOSCS
MAINF
MAINRDY
24.3.1 Main Oscillator Connections
The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typi-
cal crystal connection is illustrated in Figure 24-2. For further details on the electrical characteristics of the Main
Oscillator, see the section “DC Characteristics” of the product datasheet.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
187
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