AT91SAM7S64C-AU View Datasheet(PDF) - Atmel Corporation
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Description
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AT91SAM7S64C-AU Datasheet PDF : 775 Pages
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frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consump-
tion is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically
cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL coun-
ter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR
and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to
cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial
state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
190
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