R5F211B2DSP View Datasheet(PDF) - Renesas Electronics
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R5F211B2DSP Datasheet PDF : 339 Pages
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R8C/1A Group, R8C/1B Group
15. Serial Interface
Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Register
U0TB
U0RB
U0BRG
U0MR
U0C0
U0C1
UCON
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
U0IRS
U0RRM
CNTRSEL
Function
Set data transmission.
Data reception can be read.
Overrun error flag
Set bit rate.
Set to 001b.
Select the internal clock or external clock.
Select the count source in the U0BRG register.
Transmit register empty flag
Select TXD0 pin output mode.
Select the transfer clock polarity.
Select the LSB first or MSB first.
Set this bit to 1 to enable transmission/reception.
Transmit buffer empty flag
Set this bit to 1 to enable reception.
Reception complete flag
Select the UART0 transmit interrupt source.
Set this bit to 1 to use continuous receive mode.
Set this bit to 1 to select P1_5/RXD0/CNTR01/INT11.
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level
between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel open-
drain output), this pin is in a high-impedance state.)
Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
Function
Output serial data
Input serial data
Output transfer clock
Input transfer clock
Selection Method
(Outputs dummy data when performing reception only.)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only.)
CKDIR bit in U0MR register = 0
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
Rev.1.30 Dec 08, 2006 Page 159 of 315
REJ09B0252-0130
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