STM8S007C8T6TR(2015) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM8S007C8T6TR
(Rev.:2015)

Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C

STMicroelectronics 

Memory and register map

STM8S007C8

Table 8. General hardware register map (continued)

Address

Block

Register label

Register name

0x00 532B

TIM3_ARRH

TIM3 auto-reload register high

0x00 532C

TIM3_ARRL

TIM3 auto-reload register low

0x00 532D

0x00 532E

TIM3

TIM3_CCR1H

TIM3_CCR1L

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

0x00 532F

TIM3_CCR2H

TIM3 capture/compare register 2 high

0x00 5330

TIM3_CCR2L

TIM3 capture/compare register 2 low

0x00 5331 to

0x00 533F

Reserved area (15 bytes)

0x00 5340

TIM4_CR1

TIM4 control register 1

0x00 5341

TIM4_IER

TIM4 interrupt enable register

0x00 5342

TIM4_SR

TIM4 status register

0x00 5343

TIM4

TIM4_EGR

TIM4 event generation register

0x00 5344

TIM4_CNTR

TIM4 counter

0x00 5345

TIM4_PSCR

TIM4 prescaler register

0x00 5346

TIM4_ARR

TIM4 auto-reload register

0x00 5347 to

0x00 53FF

Reserved area (185 bytes)

0x00 5400

ADC _CSR

ADC control/status register

0x00 5401

ADC_CR1

ADC configuration register 1

0x00 5402

ADC_CR2

ADC configuration register 2

0x00 5403

0x00 5404

ADC2

ADC_CR3

ADC_DRH

ADC configuration register 3

ADC data register high

0x00 5405

ADC_DRL

ADC data register low

0x00 5406

ADC_TDRH

ADC Schmitt trigger disable register high

0x00 5407

ADC_TDRL

ADC Schmitt trigger disable register low

0x00 5408 to

0x00 57FF

Reserved area (1016 bytes)

1. Depends on the previous reset source.

2. Write only register.

Reset

status

0xFF

0xFF

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xFF

0x00

0x00

0x00

0x00

0xXX

0xXX

0x00

0x00

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DocID022171 Rev 5

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