STM8S007C8T6TR(2015) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8S007C8T6TR
(Rev.:2015)
(Rev.:2015)
STMicroelectronics
STM8S007C8T6TR Datasheet PDF : 92 Pages
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Option bytes
8
Option bytes
STM8S007C8
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 11. Option bytes
Addr.
Option
name
Option
byte no.
7
6
Option bits
5
4
3
2
1
Factory
default
0 setting
4800h
Read-out
protection
(ROP)
OPT0
ROP[7:0]
00h
4801h
4802h
User boot code OPT1
(UBC)
NOPT1
UBC[7:0]
00h
NUBC[7:0]
FFh
4803h
4804h
Alternate
function
remapping
(AFR)
OPT2
NOPT2
AFR7
AFR6
AFR5
Reserve
d
AFR3
AFR2
AFR1
AFR0
00h
NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0
FFh
4805h
4806h
Watchdog
option
OPT3
NOPT3
Reserved
Reserved
LSI
IWDG WWDG WWDG
_EN
_HW
_HW _HALT
00h
NLSI
_EN
NIWDG NWWDG NWWDG
_HW
_HW _HALT
FFh
4807h
4808h
Clock option
OPT4
NOPT4
Reserved
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
00h
NEXT NCKAW
CLK
USEL
NPR
SC1
NPR
SC0
FFh
4809h
480Ah
HSE clock
startup
OPT5
NOPT5
HSECNT[7:0]
00h
NHSECNT[7:0]
FFh
480Bh
480Ch
Reserved
OPT6
NOPT6
Reserved
00h
Reserved
FFh
480Dh
480Eh
Flash wait
states
OPT7
NOPT7
Reserved
Reserved
Wait
state
00h
Nwait
state
FFh
487Eh
OPTBL
BL[7:0]
00h
Bootloader
487Fh
NOPTBL
NBL[7:0]
FFh
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