STM8S003K3(2012) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8S003K3
(Rev.:2012)
(Rev.:2012)
STMicroelectronics
STM8S003K3 Datasheet PDF : 100 Pages
| |||
STM8S003K3 STM8S003F3
Pinout and pin description
Pin Pin
no. name
Input
Output
Main
Default
Type
function
alternate
floating wpu
Ext.
interrupt
High
sink(1)
Speed
OD
PP
(after reset) function
Alternate
function
after remap
[option bit]
28 PD3/
TIM2_CH2/
ADC_ETR
I/O X
XX
HS O3 X X Port D3
Timer 2 -
channel 2/ADC
external trigger
29 PD4/BEEP/
TIM2_CH1
I/O X
XX
HS O3 X X Port D4
Timer 2 -
channel
1/BEEP output
30 PD5/
UART1_TX
I/O X
XX
HS O3 X X Port D5
UART1 data
transmit
31 PD6/
UART1_RX
I/O X
XX
HS O3 X X Port D6
UART1 data
receive
32 PD7/ TLI
[TIM1_CH4]
I/O X
XX
HS O3 X X Port D7
Top level
interrupt
Timer 1 -
channel 4
[AFR6]
(1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings (see Electrical characteristics).
(2) When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking
up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt
is used in the application.
(3)In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not
implemented).
(4)The PD1 pin is in input pull-up during the reset phase and after internal reset release.
5.2
5.2.1
STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description
STM8S003F3 TSSOP20 pinout and pin description
Figure 4: STM8S003F3 TSSOP20 pinout
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
1
UART1_TX/AIN5/(HS) PD5
2
UART1_RX/AIN6/(HS) PD6
3
NRST
4
OSCIN/PA1
5
OSCOUT/PA2
6
VSS
7
VCAP
8
VDD
9
[SPI_NSS] TIM2_CH3/(HS) PA3
10
20 PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
19 PD2 (HS)/AIN3/[TIM2_CH3]
18 PD1(HS)/SWIM
17 PC7 (HS)/SPI_MISO [TIM1_CH2]
16 PC6 (HS)/SPI_MOSI [TIM1_CH1]
15 PC5 (HS)/SPI_SCK [TIM2_CH1]
14 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
13 PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
12
PB4 (T)/I2C_SCL [ADC_ETR]
11
PB5 (T)/I2C_SDA [TIM1_BKIN]
1. HS high sink capability.
DocID018576 Rev 3
21/100
Share Link: 