STM8S003K3 STM8S003F3
Memory and register map
Address
Block
0x00 50CC
Register label Register name
Reset
status
CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CD
CLK_SWIMCCR SWIM clock control register
0bXXXX
XXX0
0x00 50CE to
0x00 50D0
ReservLK ed area (3 bytes)
0x00 50D1
WWDG
WWDG_CR
WWDG control register
0x7F
0x00 50D2
WWDG_WR
WWDR window register
0x7F
0x00 50D3 to 00 Reserved area (13 bytes)
50DF
0x00 50E0
IWDG
IWDG_KR
IWDG key register
0xXX(2)
0x00 50E1
IWDG_PR
IWDG prescaler register
0x00
0x00 50E2
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
AWU
AWU_CSR1
AWU control/status register 1
0x00
0x00 50F1
AWU_APR
AWU asynchronous prescaler buffer
register
0x3F
0x00 50F2
AWU_TBR
AWU timebase selection register
0x00
0x00 50F3
BEEP
BEEP_CSR
BEEP control/status register
0x1F
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
0x00 5200
SPI
SPI_CR1
SPI control register 1
0x00
0x00 5201
SPI_CR2
SPI control register 2
0x00
DocID018576 Rev 3
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