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STM8S003K3(2012) View Datasheet(PDF) - STMicroelectronics

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Description
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STM8S003K3 Datasheet PDF : 100 Pages
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STM8S003K3 STM8S003F3
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Addr.
Option
name
Option Option bits
byte no.
7
6
5
4
3
2
1
Factory
default
0
setting
0x4800
Read-out
protection
(ROP)
OPT0
ROP [7:0]
0x00
0x4801 User boot OPT1 UBC [7:0]
code(UBC)
0x4802
NOPT1 NUBC [7:0]
0x00
0xFF
0x4803
0x4804
Alternate
function
remapping
(AFR)
OPT2
NOPT2
AFR7
NAFR7
AFR6 AFR5 AFR4
NAFR6 NAFR5 NAFR4
AFR3
NAFR3
AFR2 AFR1 AFR0 0x00
NAFR2 NAFR1 NAFR0 0xFF
0x4805h Miscell.
option
OPT3 Reserved
HSI
TRIM
LSI_ EN IWDG WWDG WWDG 0x00
_HW _HW _HALT
0x4806
NOPT3 Reserved
NHSI
TRIM
NLSI_
EN
NIWDG NWWDG NWW
0xFF
_HW _HW G_HALT
0x4807 Clock
option
OPT4 Reserved
EXT CLK CKAWU PRS C1 PRS C0 0x00
SEL
0x4808
NOPT4 Reserved
NEXT
CLK
NCKA NPRSC1 NPR
WUSEL
SC0
0xFF
0x4809 HSE clock OPT5 HSECNT [7:0]
startup
0x480A
NOPT5 NHSECNT [7:0]
0x00
0xFF
Option byte no.
OPT0
Table 12: Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
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