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STM8S003K3(2012) View Datasheet(PDF) - STMicroelectronics

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Description
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STM8S003K3 Datasheet PDF : 100 Pages
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Electrical characteristics
STM8S003K3 STM8S003F3
Figure 9: fCPUmax versus VDD
f
CPU
(MHz)
Functionality
not
16
guaranteed
in this area 12
8
4
0
Functionality guaranteed
@TA-40 to 85 °C
2.95
4.0
5.0
5.5
Supply voltage
Table 19: Operating conditions at power-up/power-down
Symbol Parameter
Conditions
Min Typ
VDD rise time rate
2
tVDD
VDD fall time rate(1)
2
tTEMP
Reset release delay
VDD rising
VIT+
Power-on reset threshold
2.6 2.7
VIT-
Brown-out reset threshold
2.5 2.65
VHYS(BOR) Brown-out reset hysteresis
70
Max
∞
∞
1.7
2.85
2.8
Unit
μs/V
ms
V
mV
(1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
Figure 10: External capacitor CEXT
ESR
C
ESL
Rleak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
50/100
DocID018576 Rev 3

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