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STM8S003K3U6CTR View Datasheet(PDF) - STMicroelectronics

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STM8S003K3U6CTR Datasheet PDF : 103 Pages
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Option bytes
8
Option bytes
STM8S003F3 STM8S003K3
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Addr.
Option Option
name
byte no.
7
6
Option bits
5
4
3
2
1
Factory
default
0 setting
0x4800
0x4801
0x4802
0x4803
0x4804
Read-out
protection
(ROP)
OPT0
User boot code OPT1
(UBC)
NOPT1
Alternate
function
remapping
(AFR)
OPT2
NOPT2
0x4805
0x4806
Misc. option
OPT3
NOPT3
0x4807
0x4808
Clock option
0x4809
0x480A
HSE clock
startup
OPT4
NOPT4
OPT5
NOPT5
ROP[7:0]
0x00
AFR7
AFR6
AFR5
UBC[7:0]
NUBC[7:0]
AFR4
AFR3
AFR2
AFR1
AFR0
NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0
Reserved
Reserved
Reserved
Reserved
HSITRIM
LSI
_EN
NHSI
TRIM
NLSI
_EN
EXT
CLK
NEXT
CLK
HSECNT[7:0]
NHSECNT[7:0]
IWDG
_HW
WWDG WWDG
_HW _HALT
NIWDG NWWDG NWWDG
_HW
_HW _HALT
CKAWU
SEL
PRS
C1
PRS
C0
NCKAW
USEL
NPR
SC1
NPR
SC0
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Option byte no.
OPT0
Table 13. Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
42/103
DS7147 Rev 10

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